Programmable logic arrays (PLAs) are widely used, both as packaged devices and as elements of very large scale integrated (VLSI) circuits. A PLA generally comprises an input AND array or "plane" and an output OR array interconnected by a plurality of conductors, sometimes referred to as "minterms" Input signals are applied to the input lines which enable certain of the minterm lines in accordance with the manner in which the PLA has been "programmed". The minterms then enable certain of the bit lines of the output array, again in accordance with the PLA program.
PLAs typically operate in a cyclical fashion. Application of each input signal to the AND array is controlled by a gate circuit which is enabled by a timing signal. When the input gates are enabled, the input signals propagate through the PLA and the resulting output signals are held by output latches. The period of time during which the inputs are active and the outputs are latched is generally referred to as the evaluation phase. To speed the propagation of signals in the PLA, the minterm lines and output bit lines are usually precharged to a voltage level at or near the voltage corresponding to a logical high before the input gates are enabled. The evaluation and precharge phases of the PLA are typically governed by mutually exclusive clock signals such as illustrated in FIG. 1. In a microprocessor based system, the phase clock signals of the microprocessor are conveniently used to supply such mutually exclusive clock signals.
Externally supplied clock signals may not result in optimum performance of a PLA. Consequently, a number of approaches have been taken to generate PLA timing signals internally. For example, U.S. Pat. No. 4,893,033 issued to Itano et al. discloses a PLA having an internal pulse generation circuit for providing timing pulses. The pulse generation circuit is driven by a detection circuit that senses a change in levels of the PLA input signals. As another example, U.S. Pat. No. 4,914,633 issued to Rose et al. discloses a self-timed PLA in which internally generated timing of precharging and output data latching allows the input and minterm latches to be dispensed with. A delay circuit comprises a plurality of parallel-connected transistors, the number of transistors corresponding to the maximum number of transistors connected to a minterm conductor or output bit line. Such delay ensures that valid data are captured in the output latches.
An arrangement similar to that of Rose et al. is disclosed in U.S. Pat. No. 5,003,501 issued to Podkowa. Conventional precharge timing is used, but an internal timing circuit controls the output data latches. Dedicated PLA lines that make contact to every address line and every data transistor drive the timing circuit and ensure that valid data is latched independent of process variations affecting line capacitance.
None of the above-noted prior art PLA implementations is directed to providing a low power static mode, i.e., a PLA in which the timing signals may be suspended without loss of data or high power dissipation.